FIG. 8 is a view for illustrating a configuration of a conventional semiconductor device. In the figure, in a p-type silicon layer 100, an n-type well 100a is formed. In the n-type well 100a, an n-type impurity layer 100b is formed, and through the n-type impurity layer 100b, a voltage Vdd is applied to the n-type well 100a. 
In the n-type well 100a, a p-type MOS transistor 110 and a p-type MOS varactor 120 are arranged neighboring each other. The voltage Vdd is applied to a source 113 of the p-type MOS transistor 110 and also to a source 123 and a drain 124 of the p-type MOS varactor 120.
A signal Sin is applied to a gate electrode 112 of the p-type MOS transistor 110, and a differential signal XSin of the signal Sin is input into a gate electrode 122 of the p-type MOS varactor 120. For this reason, when the p-type MOS transistor 110 is switched from ON state to OFF state or from OFF state to ON state, electric charges (for example, electrons) which have been accumulated in the channel region of the p-type MOS transistor 110 and electric charges (for example, holes) which have been accumulated in the channel region of the p-type MOS varactor 120 are exchanged. For this reason, the p-type MOS transistor 110 switches in a higher speed as compared to that of a case without p-type MOS varactor 120 (for example, refer to Patent Document 1).    Patent Document 1: Japanese Patent Laid Open No. 2002-124635 (FIG. 2)